Fpga

finite state machine

FSM – finite state machine FSM, bir vhdl kodlama metodudur. NSL next state machine decide which state to go under what conditions state’e karar verme. OFL output function logic what to do in what state under what conditions state altinda ne yapilacagina karar verme. library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity finite_state_machine is port( A: in std_logic; B: in std_logic; clock_signal: in std_logic ); end finite_state_machine; architecture finite_state_machine_a of finite_state_machine is signal x : std_logic; signal y : std_logic; constant state_a : std_logic_vector(2 downto 0) := "001"; constant state_b : std_logic_vector(2 downto 0) := "010"; constant state_c : std_logic_vector(2 downto 0) := "100"; signal state : std_logic_vector(2 downto 0) := "001"; begin process (clock_signal) begin if rising_edge(clock_signal) then case state is when state_a => x <= A; y <= B; if (x <= y) then -- --| state <= state_a; -- | else -- | NSL state <= state_b; -- | end if; -- --| when state_b => y <= A; x <= B; if ( (A or B) = '1' ) then -- --| state <= state_c; -- | else -- | NSL state <= state_b; -- | end if; -- --| when state_c => -- do nothing if (B = '1') then -- --| state <= state_a; -- | else -- | NSL state <= state_c; -- | end if; -- --| when others => state <= state; end case; end if; end process; end finite_state_machine_a; Divider Asagidaki kod simülasyona geçiyor ama orada simülasyon yapilamiyor. »

vhdl notlari

object types signal variable constant data types scalar composite file conditional statements if case when iterative statements for loop for generate while loop sup program function procedure entity entity blocks can be imagine as boxes with input and output ports. example: entity my_entity is port ( inport_1 : in std_logic; inport_2 : in std_logic; outport_1 : out std_logic; outport_2 : out std_logic ); end my_entity; bir entity architecture pair ornegi: entity and2 is port ( a : in std_logic; b : in std_logic; c : out std_logic ); end and2; architecture and2_a of and2 is begin c <= a and b after 2ns; end and2_a; entity formalize the interface »